1. Field of the Invention
The present invention relates to semiconductor devices. In particular, the present invention relates to semiconductor devices using transistors. Further, the present invention relates to display devices including the semiconductor devices, and electronic devices including the display devices.
Note that the term “semiconductor device” here includes general devices which can function by utilizing a semiconductive property.
2. Description of the Related Art
In recent years, self-luminous display devices having pixels formed with a light-emitting element such as a light-emitting diode (LED) are drawing attention. As examples of such light-emitting elements used in such self-luminous display devices, organic light-emitting diodes (also referred to as OLED (Organic Light-Emitting Diode), organic EL elements, and electroluminescence elements (also referred to as EL elements, or the like), have been drawing attention and used for EL displays or the like. Since light-emitting elements such as OLED are self-luminous type, various advantages can be provided such that high visually of pixels is ensured as compared to liquid crystal displays, no back light is required, and high response speed is achieved.
A self-luminous display device includes a display and a peripheral circuit for inputting signals to the display. By disposing a light-emitting element in each pixel of the display and controlling emission of each light-emitting element, images are displayed.
In each pixel of the display, a thin film transistor (hereinafter referred to as a TFT) is disposed. Here, a pixel configuration is described, in which two TFTs are disposed in each pixel in order to control emission of a light-emitting element in each pixel (for example, Reference 1: Japanese Published Patent Application No 2001-343933).
FIG. 15 shows a pixel configuration of a display. In a pixel portion 2100, data lines (also referred to as source signal lines) S1 to Sx, scan lines (also referred to as gate signal lines) G1 to Gy, and power source lines (also referred to as power supply lines) V1 to Vx are disposed. In addition, pixels of x (x is a natural number) columns and y (y is a natural number) rows are disposed. Each pixel includes a selection transistor (also referred to as a switching TFT, a switch transistor or a SWTFT) 2101, a driving transistor (also referred to as a driving T11) 2102, a storage capacitor 2103, and a light-emitting element 2104.
A driving method of the pixel portion 2100 is described briefly. When a scan line is selected in a selection period, the selection transistor 2101 is turned on and a potential of a data line at the time is written into a gate terminal of the driving transistor 2102 through the selection transistor 2101. In the period from termination of the selection period and to the next selection period, a potential of the gate terminal of the driving transistor 2102 is held in the storage capacitor 2103.
In the configuration of FIG. 15, when the relationship between the absolute value of a voltage between a gate and a source (|Vgs|) of the driving transistor and a threshold voltage (|Vth|) of the driving transistor 2102 satisfies |Vgs|>|Vth|, the driving transistor 2102 is turned on and a current flows by a voltage between the power source line and a counter electrode connected to the light-emitting element 2104, thereby allowing the light-emitting element 2104 to be in the emission state. Meanwhile, when |Vgs|=|Vth| is satisfied, the driving transistor 2102 is turned off and no voltage is applied to the opposite sides of the light-emitting element 2104, thereby making the light-emitting element 2104 emit no light (non-emission state).
In the pixel having the configuration of FIG. 15, two types of driving methods are generally used for expressing gray scales, which are an analog gray scale method and a digital gray scale method.
The analog gray scale method is a method for expressing gray scales by changing the luminance of a light-emitting element, using an analog signal as a signal input to each pixel. On the other hand, the digital gray scale method is a method for expressing gray scales by controlling emission or non-emission of a light-emitting element only by controlling on or off of a switching element with a signal input to each pixel.
In comparison with the analog gray scale method, the digital gray scale method is advantageous in that it is difficult to be affected by characteristic variation between TFTs, and thus gray scales can be expressed more accurately.
As an example of the digital gray scale method for expressing gray scales, there is a time gray scale method. In the time gray scale method, gray scales are expressed by controlling the emission period of each pixel of a display device. Further, by using an erasing transistor (also referred to as an erasing TFT) in addition to the driving transistor and the selection transistor in each pixel in the digital time gray scale method as disclosed in Reference 1, multi-gray scale display with high resolution can be achieved. In this specification, such a driving method is called an SES (Simultaneous Erasing Scan) drive.
In addition, in recent years, a display device having such a pixel configuration in which a memory is incorporated in each pixel of a display portion in order to reduce power consumption of the display device has been known (see Reference 2: Japanese Published Patent Application No. 2002-140034 and Reference 3: Japanese Published Patent Application No 2005-049402).
In a conventional pixel configuration disclosed in Reference 1, the power consumption of a data line driver circuit greatly depends on the charging and discharging of the last buffer. The power consumption P is generally calculated by using the following Formula (1), where F is frequency, C is capacitance, and V is voltage.P=FCV2 (F: Frequency, C: Capacitance, and V: Voltage)  (1)
According to the Formula (1), it can be seen that the voltage of a data line is preferably set to have as a small amplitude as possible by the data line driver circuit. Therefore, the voltage of a data line is set to have the minimum amplitude which allows on or off operation of the driving transistor. In other words, the absolute value of a voltage between a gate and a source (hereinafter referred to as Vgs) of the driving transistor is preferably so as to surely control the on or off operation of the driving transistor.
A potential of a data line to be input into a pixel is held in a storage capacitor in during period from termination of the selection period for turning on the selection transistor and to the next selection period for turning on the selection transistor.
However, there is such a problem that a potential that has been accumulated in the storage capacitor to be applied to the gate terminal of the driving transistor may fluctuate due to noise, leakage from the selection transistor or the like, and thus the driving transistor may malfunction without being capable of keeping the normal on or off state.
In addition, there is another problem in that the power consumption is increased if the voltage amplitude of the data line is increased in order to prevent malfunctions of the driving transistor that would be caused by fluctuation of a gate potential of the driving transistor. It can be seen from Formula (1) that the power consumption of a data line driver circuit increases in proportion to the square of a voltage; therefore, an increase in the voltage amplitude of a data line influences on the power consumption greatly.
More concretely, with reference to FIGS. 16A and 16B, problems of the conventional technique are described in detail. In the pixel configuration shown in FIG. 16A, a pixel 2200 includes a selection transistor 2201, a driving transistor 2202, a storage capacitor 2203, and a light-emitting element 2204. Note that the light-emitting element is driven with digital signals. In addition, the selection transistor is an N-channel transistor and the driving transistor is a P-channel transistor
A potential value of each wiring in FIG. 16A is described specifically. A potential of a counter electrode 2208 of the light-emitting element 2204 is GND (hereinafter, 0 V), a potential of a power source line 2207 is 7 V, a high potential level (hereinafter indicated as an High level, an High potential or High) of a data line 2206 is 7 V, a low potential level (hereinafter indicated as an Low level, an Low potential or Low) of the data line 2206 is 0 V, an High potential of a scan line 2205 is 10 V, and an Low potential of the scan line 2205 is 0 V.
Needless to say, a potential of each wiring, a polarity of each transistor and the like are just examples, and therefore, the present invention is not limited to these examples.
FIG. 16B shows a timing chart of potentials at the scan line, the data line and the node G when the light-emitting element is in the emission or non-emission state. In the period when the scan line 2205 is at 10 V, the selection transistor 2201 is turned on, and the node G receives a potential of the data line 2206. Thus, the potential of the data line 2206 is held in the storage capacitor 2203. If the potential held in the storage capacitor 2203 is the High potential, namely 7 V or higher, the voltage between the gate and source of the driving transistor 2202 becomes lower than the absolute value of the threshold voltage of the driving transistor 2202, thereby turning the driving transistor 2202 off to allow the light-emitting element 2204 to be in the non-emission state. If the potential held in the storage capacitor 2203 is the Low potential, namely 0 V or lower, the voltage between the gate and source of the driving transistor 2202 becomes higher than the absolute value of the threshold voltage of the driving transistor 2202, thereby turning the driving transistor 2202 on to allow the light-emitting element 2204 to be in the emission state.
In the pixel configuration shown herein, a potential of the data line 2206 is directly written into the node G Since the potential of the node G that is supplied from the data line 2206 controls on or off of the driving transistor 2202, at least the High potential of the data line 2206 should be equal to or higher than the potential of the power source line 2207, while the Low potential of the data line 2206 should be sufficient to turn on the driving transistor 2202. In other words, the relationship between the voltage (Vel) applied to the light-emitting element 2204 and the voltage between the source and the drain (Vds) of the driving transistor 2202 should satisfy a condition to become Vel>>Vds, which can operate the driving transistor 2202 in the linear region.
However, there is such a possibility that the potential of the node G may fluctuate due to variations or fluctuations of the threshold voltage of the driving transistor 2202, noise from outside during a holding period, a leakage potential from the selection transistor 2201 as shown in FIG. 16B, or the like, in which case the voltage between the gate and source of the driving transistor 2202 fluctuates, and thus the driving transistor 2202 may malfunction without being capable of keeping the normal on or off state.
Thus, a semiconductor device having a conventional pixel configuration has a problem in that a potential applied to the gate terminal of the driving transistor fluctuates due to noise or a leakage from the selection transistor, which causes the driving transistor to malfunction. Further, even if a signal having a large potential amplitude is supplied from a data line, which is enough to ensure the stable operation of the driving transistor, there arises another problem in that the power consumption of a data line driver circuit is increased.